Semiconductor device assemblies, including, but not limited to, memory chips, microprocessor chips, and imager chips, typically include a semiconductor device, such as a die, mounted on a substrate. The semiconductor device assembly may include various functional features, such as memory cells, processor circuits, and imager devices. The semiconductor device assembly may include semiconductor devices stacked upon and electrically connected to one another by interconnects between adjacent devices.
Various methods and/or techniques may be employed to electrically interconnect adjacent semiconductor devices and/or substrates in a semiconductor device assembly. For example, individual interconnects may be formed by reflowing tin-silver (SnAg), also known as solder, to form interconnects between the semiconductor devices. Individual interconnects may be formed by reflowing various materials such as, but not limited to, tin-silver-copper solder, indium, or the like, as would be recognized by one of ordinary skill in the art having the benefit of this disclosure.
FIG. 7 shows a prior art semiconductor device assembly 200 that includes a stack of semiconductor devices 220, 230, 240, 250 on a substrate 210. A plurality of interconnects 225, 235, 245, 255 connect the semiconductor devices 220, 230, 240, 250 to each other as well as the substrate 210. A bond tip 260 may be used to selectively position the upper most, top, or last semiconductor device 250 to the stack of semiconductor devices 240, 230, 220, as discussed herein. The withdrawal of air (not shown) through a vacuum port 263 via a flow unit 280 fluidly coupled to the vacuum port 263 via a conduit 285 creates a vacuum on the bottom surface 262, shown in FIG. 6, of the bond tip 260.
FIG. 6 is a schematic showing a bottom surface of a prior art bond tip 260. The vacuum port 263 if fluidly coupled with channels or grooves 264-271 in the bottom surface 262 of the bond tip 260. Fluidly coupling the channels 264-271 with the vacuum port 263 enables a vacuum to be formed along the bottom 262 of the bond tip 260 as air is withdrawn (not shown) via the flow device 280 (shown in FIG. 7) to selectively couple or attach a semiconductor device to the bottom surface 262 of the bond tip 260.
FIG. 7 shows the top semiconductor device 250 positioned adjacent to stack of semiconductor devices 240, 230, 220 via the bond tip 260. The withdrawal of air (not shown) creates a vacuum to selectively attach or couple the semiconductor device 250 to the bond tip 260. The semiconductor device assembly 200 is then heated to a predetermined temperature to reflow the interconnects 225, 235, 245, 255 between the semiconductor devices 220, 230, 240, 250 and the substrate 210. As the semiconductor device assembly 200 is heated, the semiconductor device 250 may assume an intrinsic warpage profile, which may result in the inadequate formation of interconnects between the top semiconductor device 250 and the adjacent semiconductor device 240. For example, the interconnects 225E along the outer edges of the semiconductor device 250 may become stretched, as shown in FIG. 7, forming inadequate interconnects between the two semiconductor devices 250, 240.
Pressure may be applied to the top surface 261 of the bond tip 260 in an effort to prevent the interconnects 255E along the outer edges or periphery of the semiconductor device 250 from stretching due to the warpage of the semiconductor device 250. Likewise, the flow device 280 may flow a fluid, shown as arrows F, through the vacuum port 263 against the top surface of the top semiconductor device 250 in an effort to prevent the interconnects 255E along the periphery of the semiconductor device 250 from stretching due to the warpage of the semiconductor device 250. However, even the applied pressure and fluid flowing, shown as arrows F, through the vacuum port 263 may not be adequate to prevent the interconnects 255E along the periphery from stretching during the reflow process.
Additional drawbacks and disadvantages may exist.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the disclosure as defined by the appended claims.